Enabling Massive Multi-threading with Fast Hashing

Alberto Scionti, Somnath Mazumdar, Stéphane Zuckerman

Research output: Contribution to journalJournal articleResearchpeer-review


The next generation of high-performance computers is expected to execute threads in orders of magnitude higher than today's systems. Improper management of such huge amount of threads can create resource contention, leading to overall degraded system performance. By leveraging more practical approaches to distribute threads on the available resources, execution models and manycore chips are expected to overcome limitations of current systems. Here, we present DELTA - a Data-Enabled muLti-Threaded Architecture, where a producer-consumer scheme is used to execute threads via complete distributed thread management mechanism. We consider a manycore tiled-chip architecture where Network-on-Chip (NoC) routers are extended to support our execution model. The proposed extension is analysed, while simulation results confirm that DELTA can manage a large number of simultaneous threads, relying on a simple hardware structure.

Original languageEnglish
JournalIEEE Computer Architecture Letters
Issue number1
Pages (from-to)1-4
Number of pages4
Publication statusPublished - Jan 2018
Externally publishedYes


  • Instruction sets
  • Computer architecture
  • Hardware
  • Computational modeling
  • Scheduling
  • Programming
  • Organizations

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